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VHDL language (www.vhdl.org) is a popular standard of designing and describing digital circuits. Hardware Description Language allows us to define a project of a digital scheme in a form of the program.
This site presents a project carried out of the Faculty of Computer Science of Technical University of Szczecin.
Its objective is to build a compiler of VHDL language, which generates a set of Boolean
equations on the basis of a VHDL source. There are certain limitations on the VHDL language,
which make possible the synthesis of logic circuits. These limitations are based on three classes
of language's constructions:
The compiler is built in accordance with the specification for Synopsys FPGA Express (http://www.synopsys.com/) and all limitations is compliant with this specification.
Previous work was sponsored by Aldec Inc. ( www.aldec.com)
Since 10th may 2002, this compiler and all additional tools is distributed under GPL License.
This project is an alpha version and propably could have some bugs and difficulties while compiling some VHDL sources.
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